EDN

Scaling down on the wings of a FinFET-DGCMOS

The double-gate (DG) FET provides a fundamental advantage over conventional single-gate (SG) FETs. In short-channel FETs the drain potential competes with that of the gate to influence the channel.
Nature

Low Power Design in CMOS and FinFET Logic Circuits

Low power design has become a cornerstone of modern integrated circuit development, driven by energy efficiency demands and the challenges of scaling in nanometre technologies. Innovations in ...
EDN

IMEC details high-k metal gate planar CMOS progress

At the IEEE International Electron Devices Meeting being held this week, Leuven, Belgium-based nanotechnology research center IMEC is reporting significant progress in improving the performance of ...
Semiconductor Engineering

The History Of CMOS

Since CMOS has been around for about 50 years, a comprehensive history would be a book. This blog focuses on what I consider the major transitions. Before CMOS, there was NMOS (also PMOS, but I have ...
ExtremeTech

Beyond 7nm and silicon: The first III-V CMOS wafers roll off production lines

Imec, perhaps the world's top semiconductor research center, has created the first monolithic III-V CMOS transistors on 300mm silicon wafers. With current silicon-based transistors hitting a wall at ...
Semiconductor Engineering

Manufacturing Bits: Oct. 26

At the upcoming IEEE International Electron Devices Meeting (IEDM) in San Francisco, a slew of entities will present papers on the latest technologies in R&D. The event, to be held Dec. 11–15, involve ...