EDN

10-Gigabit PHY devices hit new low

Both Quake Technologies and Mitsubishi have announced new 10-Gbps PHY (physical-layer) devices. Quake's third-generation, 10-Gbps QT2022 serial-to-XAUI (10-Gigabit-attachment-unit-interface) device ...
Semiconductor Engineering

Integrated Ethernet PCS And PHY IP For 400G/800G Hyperscale Data Centers

Ethernet has become the primary network protocol of choice for the required server-to-server communication in hyperscale data centers, as it allows hyperscalers to ...
Design-Reuse

GbE (10/100/1000 Base-T) PHY IP licensed by 3 different customers in Q2 alone for Worldwide Use

27 th June 22. – T2M IP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the licensing of its partner’s GbE (10/100/1000 Base-T) PHY IP Core to 3 ...
Semiconductor Engineering

A Primer For The 802.XX Physical Layer

This is the second installment of the 802.XX for the IoE series of articles. The first one was published in the August issue and addressed the Media Access Control (MAC) layer. In this article, we ...
Design-Reuse

GbE (10/100/1000Base-T) PHY IP Cores with matching 1G Ethernet MAC, PCS and TSN MAC Controller IP Cores for all your high-speed Ethernet Networking applications is available ...

2 nd May 22 – T2M IP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s GbE (10/100/1000 Base-T) PHY IP ...
EDN

FPGA PHY IP Design

This application note describes implementing and simulating the protocol-specific PHY intellectual property (IP) core in Stratix® V devices using the Interlaken PHY IP interface. You can use the ...
Business Wire

New Cadence High-Speed Ethernet Controller IP Family Enables Silicon-Proven Ethernet Subsystem Solutions up to 800Gbps

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today unveiled the Cadence ® High-Speed Ethernet Controller IP family, which enables complete Ethernet subsystem ...