The memory hierarchy (including caches and main memory) can consume as much as 50% of an embedded system power. This power is very application dependent, and tuning caches for a given application is a ...

This paper presents the architecture of a high performance level 2 cache capable of use with a large class of embedded RISC cpu cores. The cache has a number of novel features including advanced ...

While traditional single core systems employ a dedicated cache, theintroduction of multi-core platforms presents the opportunity toconsider the shared use of cache by multiple processors. Designs ...