Design-Reuse

Xilinx and EV Engineering deliver MHz co-simulation with Virtex-II technology

Based on the advanced Virtex-IITM FPGAs ZeBu accelerates co-simulation of designs driven by Verilog/VHDL/C/C++/SystemC testbenches PARIS, France, April 22, 2002 ...
Design-Reuse

Xilinx Releases ISE WebPACK 8.2i - FPGA Industry's Only Free Fully Featured Design Suite

SAN JOSE, Calif. -- July 17, 2006-- Xilinx, Inc. today announced the immediate availability of the Integrated Software Environment (ISE(TM)) WebPACK(TM) 8.2i release -- the latest version of the ...
EDN

Xilinx shipping ISE Design Suite 11.1

SAN FRANCISCO—Programmable logic vendor Xilinx Inc. is now shipping ISE Design Suite 11.1, described as the first FPGA design tool set with interoperable domain-specific design flows and tool ...
EDN

Xilinx releases ISE Design Suite 10.1

Editor”s Note: See also the related “How To” design article: Strategies for minimizing Xilinx implementation tool runtimes. In this article, author Philippe Garrault presents a variety of strategies ...
Electronic Design

Development Tool Accelerates Simulation Speed For Xilinx PGAs

Developed for Xilinx devices, the Active-HDL 4.2XE achieves a 40% increase in simulation speed over the previous 4.0XE version. Users now have the ability to seamlessly import Xilinx Foundation Series ...